# Hardware interfaces usage This chapter will describe some of the hardware features present on the NavQ+. This hardware interfaces section of the NavQPlus document is intended as a high level look at the connectors present on the board and their intended usage. Here we may also go into more detail where the interface is unique to the NavQPlus carrier board design and where it may differ from the i.MX 8M Plus EVKs. \ \ For complete in depth details regarding the IP block providing the specified interface ***please refer to NXP.com and the datasheet and reference manual for the i.MX 8m Plus system on a chip.*** --- # Agent Instructions: Querying This Documentation If you need additional information that is not directly available in this page, you can query the documentation dynamically by asking a question. Perform an HTTP GET request on the current page URL with the `ask` query parameter: ``` GET https://nxp.gitbook.io/navqplus/hardware/hardware-interfaces.md?ask= ``` The question should be specific, self-contained, and written in natural language. The response will contain a direct answer to the question and relevant excerpts and sources from the documentation. Use this mechanism when the answer is not explicitly present in the current page, you need clarification or additional context, or you want to retrieve related documentation sections.