Hardware interfaces usage

This chapter will describe some of the hardware features present on the NavQ+.

This hardware interfaces section of the NavQPlus document is intended as a high level look at the connectors present on the board and their intended usage. Here we may also go into more detail where the interface is unique to the NavQPlus carrier board design and where it may differ from the i.MX 8M Plus EVKs. For complete in depth details regarding the IP block providing the specified interface please refer to NXP.com and the datasheet and reference manual for the i.MX 8m Plus system on a chip.